The Silicon School
The path

One path into silicon — in order.

New to chips? You never have to guess what to learn next. Start at the top and climb: from the big picture to the hands-on craft. Two courses are available now; the rest of the road is on the way.

Begin here → Step 01
01
OrientationLaunching now

The Silicon World

How semiconductors really work — from a single transistor to the geopolitics of Taiwan. The map you were never given, told like a story.

All levels57 lessons~8.8hFree preview
A microchip with a tiny city built on its surface
02
Your toolsIn production

Vim & Emacs for Silicon Engineers

Master the editor you'll live inside every day — the pragmatic way, honest about both. Real speed, real muscle memory.

Hands-onwith labsexpected 2026
A cozy desk resting on a microchip, monitor with a blinking cursor
03
DesignPlanned

SystemVerilog — RTL Design

Write real, synthesizable hardware — job-ready for the design engineer, on 100% open-source tools. No paid license to follow along.

IntermediateHands-onOpen-source
Hands assembling logic-gate blocks into a chip, a waveform sketched nearby
04
VerificationPlanned

cocotb & pyUVM

Verify real chips in Python — the accessible, open-source path into the highest-paid corner of the industry.

IntermediateHands-onPython
A small robotic arm probing a chip, teal-and-yellow Python ribbons around it
05
TestLive

Silicon Test & DFT Methodologies

Make silicon testable and trustworthy: fault models and ATPG, scan and JTAG, test compression, at-speed, MBIST and low-power DFT — the senior test discipline, tool in hand. The advanced specialization.

Advanced34 lessons~5hfor ASIC/DFT pros
A microchip under fine golden test probes with a magnifier and warm lamp
The roadmap

Where this is going

The whole road into silicon — built one deliberate course at a time. Track any of these to hear the moment it opens.

Fundamentals & Design

  • VerilogThe base hardware languagePlanned
  • RTL DesignThinking in hardware: FSMs, pipelines, CDCPlanned

Verification

  • SystemVerilog for VerificationAssertions, constrained-random, coveragePlanned
  • UVMThe industry-standard methodologyPlanned
  • pyUVMUVM in PythonPlanned

Open-source implementation

  • Open-Source SimulationVerilator & IcarusPlanned
  • Practical SynthesisFrom RTL to gates with YosysPlanned
  • OpenROADRTL-to-GDS, end to endPlanned
  • OpenSTAStatic timing analysisPlanned

Deep test

  • Fault Models & ATPGThe DFT deep divePlanned

Systems

  • RISC-VFrom the ISA to a working corePlanned

Numerics & scripting

  • Octave for Digital DesignersGolden models & DSPPlanned
  • Python for Hardware EngineersAutomate the whole flowPlanned
The path is deliberate — a clear order, not an endless catalog. New to all this? Start with The Silicon World →